The present invention relates to a semiconductor device; and, more particularly, to a power-on reset circuit to produce a stable reset signal irrespective of driving speed of a power-on signal which is applied thereto at the time of its initial chip operation.
Generally, in case where a reset signal for initializing a chip is inputted through an external pin, an additional pin makes the chip go up in price. Accordingly, instead of using an additional reset pin, a circuit to generate a reset signal automatically, whenever the power is inputted into the chip, should be included in the chip itself. This circuit is called a power-on reset circuit.
FIG. 1 is a block diagram illustrating a conventional power-on reset circuit. As shown in FIG. 1, the conventional power-on reset circuit includes an input unit 110 receiving a power-on signal and outputting toggled pulse signals and a schmitt trigger 130 outputting a power-on reset signal in response to an output signal from the input unit 110.
The input unit 110 includes a capacitor C11 between an input pad of the power-on signal and node N11, an NMOS transistor NM11 which has a gate connected to node N11, a drain connected to node N11 and a source connected to a ground voltage level, a PMOS transistor PM11 which has a gate connected to node N11, a source connected to the input pad of the power-on signal and a drain connected to an output node N12, and a capacitor C12 coupled between the output node N12 and the ground voltage level.
The schmitt trigger 130 includes a schmitt trigger inverter 131 and an inverter INV11. Two PMOS transistors PM13 and PM14 are in series connected to each other and also two NMOS transistors NM13 and NM14 are in series connected to each other. Gates of these transistors PM13, PM14, NM13 and NM14 are coupled to the output node N12. A source of the PMOS transistor PM13 is connected to the input pad of the power-on signal and a drain of the PMOS transistor PM14 is connected to node N13. Accordingly, the power-on signal is transferred to node N13 in response to a voltage level at node N12. Also, a drain of the NMOS transistor NM13 is connected to the drain of the PMOS transistor PM14 and the source of the NMOS transistor NM14 is connected to the ground voltage level. A PMOS transistor PM15 in the schmitt trigger inverter 131 is coupled between the ground voltage level and a drain of the PMOS transistor PM13 and its gate is connected to node N13. Also, an NMOS transistor NM15 in the schmitt trigger inverter 131 is coupled between the source of the PMOS transistor PM13 and the source of the NMOS transistor NM13 and its gate is connected to node N13 which provides an input for the inverter INV11.
FIG. 3A is a voltage wave form of the conventional schmitt trigger in FIG. 1 and FIG. 3B is a hysteresis loop illustrating voltage transfer characteristics for the conventional schmitt trigger in FIG. 1.
Referring to FIG. 3A, the schmitt trigger inverter inverts the input signal VIN, by using a first voltage level VID as a reference voltage level for determining a high voltage level and a second voltage level VIU as a reference voltage level for determining a low voltage level. As a result, in case where the input signal VIN is larger than the first voltage level VID, the input signal VIN is considered as a high voltage level and, in case where the input signal VIN is smaller than the second voltage level VIU, the input signal VIN is considered as a low voltage level. Accordingly, when the input signal VIN is between the first voltage level VID and the second voltage level VIU, the schmitt trigger inverter may not positively work as an inverter. Accordingly, the schmitt trigger inverter doesn""t have an effect on its output in case where there is a voltage variation between the first voltage level VID and the second voltage level VIU based on a glitch which is caused by a sudden increases in the supply of electric power.
Also, as shown in FIG. 3B, in case where the input signal VIN is in the vicinity of the first voltage level VID and the second voltage level VIU, the schmitt trigger inverter produces a dramatically inverted output signal irrespective of transition time of the input signal VIN. As set forth above, the schmitt trigger inverter has been used in improving the transition of the slow signal and in removing an input noise. Referring again to FIG. 1, when the activated power-on signal is applied to the capacitor C11, a potential at node N11 rapidly increases in response to the power-on signal. Accordingly, the NMOS transistor NM11 is turned on, node N11 gradually goes into a pull-down mode, and then finally, the NMOS transistor NM11 may be turned off. When the PMOS transistor PM11 is turned on with the pull-down operation at node N11, the capacitor C12 is charged and the output node N12 of the input unit 110 is in a pull-up mode in such a way as to toggle the voltage level of the output node N12. After the output node N12 in the input unit 110 is toggled once, node N11 gradually goes into a pull-up mode and the PMOS transistor PM11 is turned on and the output node N12 goes into a pull-down mode. Namely, the output node N12 of the input unit 110, as an input signal of the schmitt trigger 130, gradually goes from xe2x80x9clow voltage levelxe2x80x9d to xe2x80x9chigh voltage levelxe2x80x9d or from xe2x80x9chigh voltage levelxe2x80x9d to xe2x80x9clow voltage levelxe2x80x9d.
If the output node N12 of the input unit 110 gradually goes from xe2x80x9clow voltage levelxe2x80x9d to xe2x80x9chigh voltage level,xe2x80x9d the schmitt trigger inverter 131 outputs an inverted low voltage level signal at the time when the input signal is higher than the first voltage level VID and, when the output node N12 of the input unit 110 gradually goes from xe2x80x9chigh voltage levelxe2x80x9d to xe2x80x9clow voltage levelxe2x80x9d and when the input signal is lower than the second voltage level VIU, the schmitt trigger inverter 131 outputs a toggled output signal from xe2x80x9chigh voltage levelxe2x80x9d to xe2x80x9clow voltage level.
FIG. 2 is a block diagram illustrating another conventional power-on reset circuit. The power-on reset circuit in FIG. 2 includes an input unit 210 to produce toggled signals in response to power-on signal, a schmitt trigger inverter 231 outputting a power-on reset signal in response to the toggled signals and a feed-back loop 270 feeding back an output signal of the schmitt trigger inverter 231 to the input unit 210.
The input unit 210 has a PMOS transistor PM21, an NMOS transistor NM21 and a capacitor C21. The PMOS transistor PM21 receives an voltage level at node N20 through its gate and transfers a power-on signal to a node 21. The NMOS transistor NM21 receives an voltage level at node N20 through its gate and transfers a ground voltage level to the node 21. Also, the capacitor C21, which is a MOS transistor having source and drain connected to a ground voltage level, is connected to the node 21. A schmitt trigger inverter 231 is the same as that (the reference numeral 131) in FIG. 1. An output unit 250 connected to an output terminal (node N23) of the schmitt trigger inverter 231 latches and buffers an output signal of the schmitt trigger inverter 231, having a plurality of inverters INV21 to INV25. Further, the feed-back loop 270 includes an inverter INV28 inverting a signal at node N20, an NAND gate ND27 receiving output signals from the inverter INV28 and the schmitt trigger inverter 231, and inverters INV26 and INV27 for buffering an output signal of the NAND gate ND27.
When the power-on signal is activated, the PMOS transistor PM21 is turned on by a low voltage level which is inputted into node N20 and the MOS capacitor C21 charges electric carriers. Accordingly, the output node N23 gradually goes from a low voltage level to a high voltage level and the output terminal of the schmitt trigger inverter 131 is toggled from a high voltage level to a low voltage level. Also, the output signal of schmitt trigger inverter 231 is latched and buffered at the output unit 250 and activates the power-on reset signal in a low voltage level.
The output signal of schmitt trigger inverter 231, which is in a high voltage level, is feed back to the input unit 210 through the feed back loop 270 so that such a feed-back signal makes the power-on reset signal (POR) in a high voltage level. The signal at node N20 is continuously inputted into the feed back loop 270 in a high voltage level and therefore the power-on reset signal is maintained in a high voltage level.
However, in case where it takes a long time (a few microsecondsxe2x80x94a few milliseconds) to turn on the power-on reset circuit after power is applied to it, the power-on reset circuit can not normally operate.
In case of the power-on reset circuit in FIG. 1, the power-on reset circuit does not work until the power-on signal goes up to the desired power within 10. If the power-on signal is slowly applied to the power-on reset circuit, charges are stored in the capacitor C11 and node N21 doesn""t comply with the power-on signal. As a result, the output node N23 is not toggled so that the reset signal may not be produced.
Also, in the power-on reset circuit of FIG. 2, if the input time of the power-on signal is long, the PMOS transistor PM21 is turned on in response to the signal at node N20 in the input unit 210 and, before the output node N21 is in a high voltage level, node N21 is continuously maintained in a high voltage level by the feed-back loop 270. After a predetermined time, node N21 is in a low voltage level and such a low voltage level is continuously maintained with the toggle of the power-on reset signal (POR).
However, since most of the expensive instruments is gradually turned on in order to prevent a damage, this long power-on time may interrupt a normal operation of the power-on reset circuit.
It is, therefore, an object of the present invention to provide power-on reset circuit producing stable reset signals irrespective of power-on time applied to it.
In accordance with an aspect of the present invention, there is provided a power-on reset circuit for producing a power-on reset signal in response to a power-on signal which is activated when power is applied to a chip in a semiconductor device, the power-on reset circuit comprising: an input means receiving the power-on signal from an external circuit; a first inverting means including an output node, wherein a voltage level at the output node is toggled from a high voltage level signal to a low voltage level signal before an output signal from the input means increases up to a desired voltage level; and a means coupled to the output node for generating the power-on reset signal in response to the voltage level at the output node.